Technology computer-aided design simulation of Ge-source double-gate Si-tunnel Field Effect Transistor: Radio frequency and linearity analysis

This article presented a thorough investigation of direct current (DC), analog/radio frequency (RF), and linearity performance of a proposed Ge-source double gate planner Si-tunnel field-effect transistor (TFET) considering different parameter variations using Sentaurus TCAD 2-D device simulator. The analyses are performed using various quality matrices such as transconductance (g(m)), total gate capacitance (C-gg), unity gain cut-off frequency (f(T)), gain-bandwidth product (GBP), transconductance frequency product (TFP), etc. It can be perceived that the inclusion of source/channel junction pocket, low bandgap source material, high k gate dielectric, and dual k spacer technology can improve the TFET performances in terms of on-current (I-ON), off-current (I-OFF), on-off current ratio (I-ON/ I-OFF) and subthreshold swing (SS) at a supply voltage V-DS = 0.7 V. In this article, we used a non-quasi-static (NQS) small-signal model to analyze the behavior of the proposed device in high-frequency regions. Based on this, the small-signal admittance parameters were validated up to 1 THz. The proposed TFET produced RF figures of merit (FoM), cut-off frequency (f(T)), and maximum oscillation frequency (f(max)) in the terahertz range at V-DS = V-GS = 1 V. Linearity and distortion parameters considered here are VIP2 (interpolated input voltage at which first and second harmonics are equal), VIP3 (interpolated input voltage at which first and third harmonics are similar), IIP3 (third-order input intercept point), IMD3 (third-order intermodulation distortion), 1-dB compression point, HD2 (second-order harmonic), HD3 (third-order harmonic) and THD (total harmonic distortion) for different supply voltages. According to the study, the proposed TFET can provide improved RF and linearity performance, ensuring device reliability in low-power, high-frequency applications.