Horizontal diversity in test generation for high fault coverage

被引:2
|
作者
Alamgir, Arbab [1 ]
Bin A'Ain, Abu Khari [1 ,2 ]
Paraman, Norlina [1 ]
Sheikh, Usman Ullah [1 ]
Grout, Ian [3 ]
机构
[1] Univ Teknol Malaysia, Fac Engn, Sch Elect Engn, Johor Baharu, Malaysia
[2] Univ Tun Hussein Onn, Inst Integrated Engn, Batu Pahat, Malaysia
[3] Univ Limerick, Fac Sci & Engn, Dept Elect & Comp Engn, Limerick, Ireland
关键词
Antirandom; test pattern generation; computations reduction; horizontal Hamming distance; vertical Hamming distance; IN SELF-TEST; SCHEME; BIST;
D O I
10.3906/elk-1805-212
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Determination of the most appropriate test set is critical for high fault coverage in testing of digital integrated circuits. Among black-box approaches, random testing is popular due to its simplicity and cost effectiveness. An extension to random testing is antirandom that improves fault detection by maximizing the distance of every subsequent test pattern from the set of previously applied test patterns. Antirandom testing uses total Hamming distance and total cartesian distance as distance metrics to maximize diversity in the testing sequence. However, the algorithm for the antirandom test set generation has two major issues. Firstly, there is no selection criteria defined when more than one test pattern candidates have the same maximum total Hamming distance and total cartesian distance. Secondly, determination of total Hamming distance and total Cartesian distance is computational intensive as it is a summation of individual Hamming distances and cartesian distances with all the previously selected test patterns. In this paper, two-dimensional Hamming distance is proposed to address the first issue. A novel concept of horizontal Hamming distance is introduced, which acts as a third criterion for test pattern selection. Fault simulations on ISCAS'85 and ISCAS'89 benchmark circuits have shown that employing horizontal Hamming distance improves the effectiveness of pure antirandom in terms of fault coverage. Additionally, an alternative method for total Hamming distance calculations is proposed to reduce the computational intensity. The proposed method avoids summation of individual Hamming distances by keeping track of number of 0s and is applied at each inputs. As a result, up to 90% of the computations are reduced.
引用
收藏
页码:3258 / 3273
页数:16
相关论文
共 50 条
  • [41] Real-time java API specifications for high coverage test generation
    Ahrendt, Wolfgang
    Mostowski, Wojciech
    Paganelli, Gabriele
    ACM International Conference Proceeding Series, 2012, : 145 - 154
  • [42] A Test Scenario Generation Method for High Requirement Coverage by using KAOS method
    Fujikura, Toshiyuki
    Kurachi, Ryo
    2019 COMPANION OF THE 19TH IEEE INTERNATIONAL CONFERENCE ON SOFTWARE QUALITY, RELIABILITY AND SECURITY (QRS-C 2019), 2019, : 542 - 543
  • [43] RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
    M.B. Santos
    F.M. Gonçalves
    I.C. Teixeira
    J.P. Teixeira
    Journal of Electronic Testing, 2002, 18 : 179 - 187
  • [44] RTL design validation, DFT and test pattern generation for high defects coverage
    Santos, MB
    Gonçalves, FM
    Teixeira, IC
    Teixeira, JP
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2002, 18 (02): : 179 - 187
  • [45] Test Pattern Generation for Crosstalk Fault of High-speed Interconnect
    Shang Yuling
    Li Yushan
    PROCEEDINGS OF THE 12TH WSEAS INTERNATIONAL CONFERENCE ON CIRCUITS: NEW ASPECTS OF CIRCUITS, 2008, : 255 - +
  • [46] A test cases generation method for FSM with counters and its fault coverage evaluation using a mutant generator
    Kohara, M
    Higuchi, M
    Fujii, M
    1997 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS 1 AND 2: PACRIM 10 YEARS - 1987-1997, 1997, : 555 - 559
  • [47] ASIC TESTING WITH HIGH FAULT COVERAGE
    BUTZERIN, T
    SAMAD, A
    ARCHAMBEAU, E
    VLSI SYSTEMS DESIGN, 1988, 9 (09): : 50 - &
  • [48] HIGH FAULT COVERAGE ISNT ENOUGH
    GOMES, K
    COMPUTER DESIGN, 1992, 31 (09): : 62 - &
  • [49] A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint
    Inoue, Ryoichi
    Hosokawa, Toshinori
    Fujiwara, Hideo
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2010, E93D (01): : 24 - 32
  • [50] Test Vector Omission for Fault Coverage Improvement of Functional Test Sequences
    Pomeranz, Irith
    IEEE TRANSACTIONS ON COMPUTERS, 2015, 64 (11) : 3317 - 3321