Microeconomics of overlay control at the 65nm technology node

被引：2
|
作者：
Allgair, JA [1 ]
Monahan, KM [1 ]
机构：
[1] Motorola Inc, Dan Noble Ctr, Austin, TX 78721 USA
来源：
2003 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/ISSM.2003.1243241
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
ITRS working groups have identified overlay control as a technology roadblock with no known solutions at the 65nm node and beyond. The most serious problems are total measurement uncertainty, CMP process robustness, and device correlation. A systematic root-cause analysis of pattern placement error (PPE) at Motorola's Dan Noble Center has determined that current box-in-box overlay targets cause deficiencies in all three categories. A Proposed solution utilizes advanced imaging targets that are grating-based and can be segmented with features that are similar to those in the device. In the case of poly-to-STI overlay using 193nm lithography tools, these targets show a 40% decrease in total measurement uncertainty.
引用
收藏
页码：103 / 106
页数：4
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