Implementation on FPGA of a lut-based ATAN(Y/X) operator suitable for synchronization algorithms

被引：7
|
作者：
Gutierrez, Roberto
Valls, Javier
机构：
来源：
2007 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLS 1 AND 2 | 2007年
关键词：
D O I：
10.1109/FPL.2007.4380692
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture is based on LUT methods and achieves lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm with a lower latency. The proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC with the same latency.
引用
收藏
页码：472 / 475
页数：4
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