Implementation on FPGA of a lut-based ATAN(Y/X) operator suitable for synchronization algorithms

被引：7
|
作者：
Gutierrez, Roberto
Valls, Javier
机构：
来源：
2007 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLS 1 AND 2 | 2007年
关键词：
D O I：
10.1109/FPL.2007.4380692
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture is based on LUT methods and achieves lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm with a lower latency. The proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC with the same latency.
引用
收藏
页码：472 / 475
页数：4
相关论文
共 50 条
  • [31] Efficient LUT-based FPGA technology mapping for power minimization
    Hao, L
    Mak, WK
    Katkoori, S
    ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2003, : 353 - 358
  • [32] SPFD-based flexible transformation of LUT-based FPGA circuits
    Tanaka, K
    Yamashita, S
    Kambayashi, Y
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2005, E88A (04) : 1038 - 1046
  • [33] LUT-Based QCA Implementation of a 4x4 S-Box
    Amiri, Mohammad Amin
    Mahdavi, Mojdeh
    Mirzakuchaki, Sattar
    IEEE TIC-STH 09: 2009 IEEE TORONTO INTERNATIONAL CONFERENCE: SCIENCE AND TECHNOLOGY FOR HUMANITY, 2009, : 996 - 999
  • [34] Direct mapping of RTL structures onto LUT-based FPGA's
    Naseer, AR
    Balakrishnan, M
    Kumar, A
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1998, 17 (07) : 624 - 631
  • [35] Partitioning Strategy for LUT-based Applications Using Genetic Algorithms
    Mehdi, Riyadh A. K.
    Khali, H.
    2009 IEEE/ACS INTERNATIONAL CONFERENCE ON COMPUTER SYSTEMS AND APPLICATIONS, VOLS 1 AND 2, 2009, : 896 - +
  • [36] LUT-based FPGA technology mapping for power minimization with optimal depth
    Li, H
    Mak, WK
    Katkoori, S
    IEEE COMPUTER SOCIETY WORKSHOP ON VLSI 2001, PROCEEDINGS, 2001, : 123 - 128
  • [37] Highly efficient, limited range multipliers for LUT-based FPGA architectures
    Turner, RH
    Woods, RF
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (10) : 1113 - 1117
  • [38] Technology mapping of multi-output function into LUT-based FPGA
    Kubica, Marcin
    Milik, Adam
    Kania, Dariusz
    IFAC PAPERSONLINE, 2018, 51 (06): : 107 - 112
  • [39] Technology mapping for delay-minimization in LUT-based FPGA designs
    Peng, YX
    Chen, XC
    Li, SK
    FIFTH INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN & COMPUTER GRAPHICS, VOLS 1 AND 2, 1997, : 572 - 575
  • [40] Implementation of OFDM Frame Synchronization Algorithms Based on FPGA Design
    Jing, Qing-feng
    Cheng, Ming
    Yan, Xiao-ju
    Kong, Fan-qiang
    2015 INTERNATIONAL CONFERENCE ON SOFTWARE, MULTIMEDIA AND COMMUNICATION ENGINEERING (SMCE 2015), 2015, : 191 - 196
12345