Exploring the Feasibility of Implementing Negative-Capacitance Tunnel-FET (NC-TFET) in Low-Power Digital Circuits

被引：0

作者：

Guha, Sourav ^{[1
]}

Pachal, Prithviraj ^{[2
]}

机构：

[1] Jadavpur Univ, Dept Elect & Tele Commun Engn ETCE, Kolkata, India

[2] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL USA

来源：

PROCEEDINGS OF 3RD IEEE CONFERENCE ON VLSI DEVICE, CIRCUIT AND SYSTEM (IEEE VLSI DCS 2022) | 2022年

关键词：

ferroelectric; inverter; ring-oscillator; Tunnel-FET;

D O I：

10.1109/VLSIDCS53788.2022.9811449

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper attempts to highlight the circuit-level performance of negative-capacitance tunnel FET, when implemented in low-voltage (V-DD) digital logic circuits. SILVACO TCAD is used to simulate the device and properly fitted with L-K calculated solution. The voltage amplification effect on the device current characteristics, corresponding to the ferroelectric gate layer has been suitably presented in this paper. Cadence Virtuoso has been utilized to implement various circuit level applications using NCTFET and suitably benchmarked with a conventional reference TFET (R-TFET). This paper presents the significant advantages gained by implementation of NCTFET in low power circuits.

引用

页码：1 / 4

页数：4

共 25 条

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