Exploring the Feasibility of Implementing Negative-Capacitance Tunnel-FET (NC-TFET) in Low-Power Digital Circuits

This paper attempts to highlight the circuit-level performance of negative-capacitance tunnel FET, when implemented in low-voltage (V-DD) digital logic circuits. SILVACO TCAD is used to simulate the device and properly fitted with L-K calculated solution. The voltage amplification effect on the device current characteristics, corresponding to the ferroelectric gate layer has been suitably presented in this paper. Cadence Virtuoso has been utilized to implement various circuit level applications using NCTFET and suitably benchmarked with a conventional reference TFET (R-TFET). This paper presents the significant advantages gained by implementation of NCTFET in low power circuits.