A reconfigurable two-stage cyclic ADC for low-power applications in 3.3V 0.35μm CMOS

This article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1kHz to 40MHz. The circuit has been prototyped in a 3.3V 0.35 mu m CMOS process and consumes 14.1mW at 40MHz and 8MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1dB SNR, 56.57dB SINAD and 9.1 bit ENOB at 0.666MHz input frequency and 53.6dB SNR, 52.4dB SINAD and 8.6 bit ENOB at 3.85MHz input frequency. The technological FOM obtained was 13.2As/m(2).