System-in-package integration of passives using 3D through-silicon vias

被引：0
|
作者：
Roozeboom, F. [1 ]
Dekkers, W. [1 ]
Lamy, Y. [1 ]
Klootwijk, J. H. [2 ]
van Grunsven, E. [2 ]
Kim, H. -D. [3 ]
机构：
[1] NXP TSMC Res Ctr, NL-5656 AE Eindhoven, Netherlands
[2] Philips Res Labs, Eindhoven, Netherlands
[3] Jusung Engn Co Ltd, Gyunggi Do, South Korea
来源：
SOLID STATE TECHNOLOGY | 2008年 / 51卷 / 05期
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Future generations of cellular RF transceivers require higher degrees of integration, preferably using the third dimension. System-in-Package (SiP) applications have been shown for integrated 3D "trench" capacitors in silicon with a new world record capacitance density of >= 400F/mm(2) and break-down voltage >6V using Atomic Layer Deposition (ALD) of multiple MIM layer stacks of high-k dielectrics (Al2O3) and conductive layers (TiN). Different techniques may be used for through-silicon via (TSV) drilling and filling to allow for 3D die and wafer stacking with a small form factor. Both dry and we methods were applied successfully in both the drilling and fill electrochemical etching yields ultrafine high aspect ratio (similar to 1.5 mu mx200 mu m) vias. A new "bottom-up" Cu-electroplating method and some preliminary Cu-paste filling tests show options for via metal formation.
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页码：38 / +
页数：5
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