An Efficient Architecture for Accurate and Low Power CMOS Analog Multiplier

A new analog four-quadrant multiplier in CMOS technology is proposed using translinear loops (TLs). The novelty of the work includes an improved structure resulting in high precision output, low power consumption and low body effect error. The higher accuracy is achieved using a symmetrical arrangement of the proposed multiplier, where the errors on the two sides of circuit are subtracted from each other. The simple structure, as well as the sharing bias branch in the squaring circuits, leads to the low power dissipation of the multiplier circuit. In addition, the proposed circuit is thoroughly analyzed in terms of the body effect error and the results are presented. In order to validate the performance of the circuit, the designed multiplier is used in two useful applications: frequency doubler and amplitude modulator. The post layout simulation results of the circuit are performed using Cadence Virtuoso and HSPICE with level 49 parameters (BSIM3v3) of TSMC 0.18 mu m technology. The results show a nonlinearity of 0.93%, a total harmonic distortion (THD) of 0.98% at a frequency of 1MHz, a -3dB bandwidth of 736MHz and a maximum power dissipation of 0.0619mW.