An efficient bus architecture for system-on-chip design

被引：26
|
作者：
Cordan, B [1 ]
机构：
[1] PALMCHIP Corp, Colorado Design Ctr, Loveland, CO USA
来源：
PROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 1999年
关键词：
D O I：
10.1109/CICC.1999.777358
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents the issues confronted when integrating system-on-chip (SOC) designs and offers solution through a detailed description of the CoreFrame(TM) system-on-chip bus architecture that has dramatically reduce system design and verification effort while enhancing the reusability and customizability of system-on-chip product developments. The CoreFrame on-chip bus architecture is defined along with examples to illustrate how a design friendly bus standard will effect the mix and match of reusable cores without sacrificing performance.
引用
收藏
页码：623 / 626
页数：4
相关论文
共 50 条
  • [1] Efficient bus architecture for system-on-chip design
    Cordan, Bill
    Proceedings of the Custom Integrated Circuits Conference, 1999, : 623 - 626
  • [2] A TROJAN-RESISTANT SYSTEM-ON-CHIP BUS ARCHITECTURE
    Kim, Lok-Won
    Villasenor, John D.
    Koc, Cetin K.
    MILCOM 2009 - 2009 IEEE MILITARY COMMUNICATIONS CONFERENCE, VOLS 1-4, 2009, : 2452 - +
  • [3] System-on-chip design with dataflow architecture
    Wu, BF
    Peng, CL
    PROCEEDINGS OF THE 8TH INTERNATIONAL CONFERENCE ON COMPUTER SUPPORTED COOPERATIVE WORK IN DESIGN, VOL 2, 2004, : 712 - 716
  • [4] Reliable and efficient system-on-chip design
    Shanbhag, NR
    COMPUTER, 2004, 37 (03) : 42 - +
  • [5] Design of an architecture for Multiprocessor System-on-Chip (MPSoC)
    Hu Yue-li
    Ding Qian
    2006 CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP '06), PROCEEDINGS, 2006, : 267 - +
  • [6] Design methodology of a configurable system-on-chip architecture
    Wallner, S
    12TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, 2004, : 283 - 284
  • [7] Efficient exploration of bus-based system-on-chip architectures
    Kim, Sungchan
    Ha, Soonhoi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2006, 14 (07) : 681 - 692
  • [8] System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies
    Wang, N.
    Bayoumi, M. A.
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2007, 1 (01): : 1 - 8
  • [9] A System-On-Chip Bus Architecture for Thwarting Integrated Circuit Trojan Horses
    Kim, Lok-Won
    Villasenor, John D.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (10) : 1921 - 1926
  • [10] A system-on-chip bus architecture for hardware Trojan protection in security chips
    Liu, Changlong
    Zhao, Yiqiang
    Shi, Yafeng
    Gao, Xingbo
    2011 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2011, 2011,
12345