DFT Technique for Quick Characterization of Flash Offset in Pipeline ADCs

被引：0
|
作者：
Nair, Pradeep [1 ]
Viswanathan, Nagarajan [1 ]
机构：
[1] Texas Instruments India Pvt Ltd, Bangalore, Karnataka, India
来源：
2015 28TH INTERNATIONAL CONFERENCE ON VLSI DESIGN (VLSID) | 2015年
关键词：
Sample and Hold Amplifier (SHA); Multiplying Digital to Analog Converter (MDAC); Process; Voltage and Temperature (PVT); Differential Non-Linearity (DNL);
D O I：
10.1109/VLSID.2015.69
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper proposes a novel DFT block and associated method for characterizing the offsets of the coarse flash used in a pipelined ADC. In non-SHA architecture, due to the presence of dynamic offset, measuring flash offsets across input frequency becomes important. By adding special data output modes, the proposed DFT technique allows speedy characterization of flash offset, across PVT, using the standard single-tone test and measurement setup [1][2] for the ADCs.
引用
收藏
页码：375 / 380
页数：6
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