An 8-bit 208 MS/s SAR ADC in 65 nm CMOS

被引：1

作者：

Zhu, Zhangming ^{[1
]}

Wang, Qiyu ^{[1
]}

Xiao, Yu ^{[1
]}

Song, Xiaoli ^{[1
]}

Yang, Yintang ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, Xian 710071, Peoples R China

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2013年 / 76卷 / 01期

基金：

中国国家自然科学基金;

关键词：

Successive approximation register (SAR) A/D converter; High speed; CMOS; Reused terminating capacitor switching; SUCCESSIVE-APPROXIMATION ADC;

D O I：

10.1007/s10470-013-0071-5

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An 8-bit low-power 208MS/s SAR analog-to-digital converter is presented. To achieve a high-speed and low-power operation, a reused terminating capacitor switching procedure is proposed. The proposed switching procedure halves the capacitors leading to a significant power saving over the conventional one. Moreover, the proposed architecture relaxes the settling time of DAC and subsequently improves the conversion rate. The ADC has been simulated in SMIC 65 nm 1.2 V CMOS technology. At a 1.2-V supply and 208 MS/s, the ADC consumes 2.7 mW and achieves an SNDR of 49.6 dB, an SFDR of 61.0 dB with 100 MHz inputs.

引用

页码：129 / 137

页数：9

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