A background calibration in pipelined ADCs

被引：9

作者：

Mafi, Hamid R. ^{[1
]}

Sodagar, Amir M. ^{[2
,3
,4
]}

机构：

[1] Azad Univ, Qazvin Branch, Dept Elect Engn, Barajin, Qazvin, Iran

[2] KN Toosi Univ Technol KNTU, Dept Elect Engn, Res Lab Integrated Circuits & Syst ICAS, Tehran, Iran

[3] Polytech Montreal, Montreal, PQ, Canada

[4] Inst Res Fundamental Sci, Sch Cognit Sci, Tehran, Iran

来源：

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2013年 / 67卷 / 08期

关键词：

Background calibration; Pipelined analog to digital converters; (ADCs); Pseudorandom sequence; CMOS ADC; CONVERSION;

D O I：

10.1016/j.aeue.2013.03.005

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a novel background calibration is presented. The proposed scheme continuously measures and digitally compensates conversion errors caused by residue amplifier nonlinearity. This scheme can be used to relax analog circuit requirements for high-precision residue amplifier, accordingly decreasing the power consumption and/or increasing sampling rates in pipelined ADCs. The proposed scheme employs a fifth-order polynomial to eliminate conversion errors. One unique feature of the proposed scheme is that a single pseudorandom sequence, pn, is exploited. The simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion-ratio (SNDR) is improved from 40 to 66 dB and the spurious-free-dynamic-range (SFDR) is increased from 48 to 80 dB. (C) 2013 Elsevier GmbH. All rights reserved.

引用

页码：729 / 732

页数：4

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