FPGA-based fault injection for microprocessor systems

In this paper we propose an approach to speed-up Fault Injection campaigns for the evaluation of dependability properties of processor-based systems. The approach exploits FPGA devices for system emulation, and new techniques are described, allowing emulating the effects of faults and to observe faulty behavior. The proposed approach combines the speed of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that speed-up figures up to 3 orders of magnitude with respect to state-of-the-art simulation-based techniques can be achieved.