FPGA-based fault injection for microprocessor systems

被引：13

作者：

Civera, P ^{[1
]}

Macchiarulo, L ^{[1
]}

Rebaudengo, M ^{[1
]}

Reorda, MS ^{[1
]}

Violante, M ^{[1
]}

机构：

[1] Politecn Torino, Dipartimento Automat & Informat, I-10129 Turin, Italy

来源：

10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ATS.2001.990301

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we propose an approach to speed-up Fault Injection campaigns for the evaluation of dependability properties of processor-based systems. The approach exploits FPGA devices for system emulation, and new techniques are described, allowing emulating the effects of faults and to observe faulty behavior. The proposed approach combines the speed of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that speed-up figures up to 3 orders of magnitude with respect to state-of-the-art simulation-based techniques can be achieved.

引用

页码：304 / 309

页数：6

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