VLSI implementation of fractal image compression processor for moving pictures

This paper proposes an efficient VLSI architecture of fractal image coding for moving pictures. The proposed processor makes use of parallel searching for similar domain blocks by grouping range blocks by identical classes. Furthermore, to a encode moving picture at high-speed, utilizing the domain block information obtained in the coding of a previous frame to code the following frame is employed. According to this architecture, a smaller fractal image coding VLSI can be realized. The architecture is capable of high-speed, real-time encoding not only for still images but also for full-motion pictures using a circuit size. The compression ratios are 2-5 times higher: and the code processing tithe is 10 times faster than those of conventional fractal techniques. The adoption of the proposed VLSI architecture technique achieves real-tittle encoding of, full-motion videos, anti the circuit size of VLSI is much smaller than previously proposed fractal processors.