A high-speed offset cancelling distributed sample-and-hold architecture for flash A/D converters

被引：2

作者：

Mountrichas, L. ^{[1
]}

Siskos, S. ^{[1
]}

机构：

[1] Aristotle Univ Thessaloniki, Dept Phys, Elect Lab, Thessaloniki 54125, Greece

来源：

MICROELECTRONICS JOURNAL | 2013年 / 44卷 / 12期

关键词：

Analog-to-digital converter; Distributed; High-speed; Offset storage; Sample-and-hold; ADC; DESIGN;

D O I：

10.1016/j.mejo.2013.06.016

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 6-bit high-speed analog-to-digital converter was implemented utilizing a novel distributed sample-and-hold architecture capable of sampling and subtracting the input preamplifier's offset. This architecture offers substantial improvement in the high-speed operation of the converter. Compared to the prior-art, the effective number of bits improves 0.8 bit. The spurious free dynamic range improvement is over 12 dB. In addition the implemented technique uses half the number of capacitors compared to similar designs. The converter achieves over 5.2 bit resolution up to the Nyquist input signal frequency. A simple but effective design methodology is also presented. (C) 2013 Elsevier Ltd. All rights reserved.

引用

页码：1123 / 1131

页数：9

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