A Low Power Low Latency Comparator for Ramp ADC in CMOS Imagers

被引：0

作者：

Kaur, Amandeep ^{[1
]}

Sarkar, Mukul ^{[1
]}

机构：

[1] Indian Inst Technol Delhi, Dept Elect Engn, Delhi, India

来源：

2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2016年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low latency and a low power comparator is presented in this paper. The concept of current aiding at the output nodes of SR latch is proposed to enhance the switching speed of the comparator. The current flowing through the output nodes of regenerative latch is sensed and the amplified difference of these two currents is applied to the output nodes of SR latch. The circuit is designed and simulated in UMC 180 nm CMOS technology. Circuit consumes total power of 4.289 mu W while operating at the clock frequency of 20 MHz. Measurement results proved that the designed comparator requires maximum of three clock cycles to perform switching for the input range 250-850 mV.

引用

页码：1466 / 1469

页数：4

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