A BISR architecture for embedded memories

被引：6

作者：

Pekmestzi, Kiamal ^{[1
]}

Axelos, Nicholas ^{[1
]}

Sideris, Isidoros ^{[1
]}

Moshopoulos, Nicolaos ^{[1
]}

机构：

[1] Natl Tech Univ Athens, Sch Elect & Comp Engn, GR-10682 Athens, Greece

来源：

14TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/IOLTS.2008.21

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities. On a 4Mbit memory and an average number of 1024 memory defects per IC, a repair ratio of 100% and over 90% require less than 2% and 1% memory overhead respectively.

引用

页码：149 / 154

页数：6

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