New improved 1-bit full adder cells

被引：0
|
作者：
Veeramachaneni, Sreehari [1 ]
Srinivas, M. B. [1 ]
机构：
[1] Int Inst Informat Technol, Ctr VLSI & Embedded Syst Technol CVEST, Hyderabad, Andhra Pradesh, India
来源：
2008 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-4 | 2008年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The 1-bit full adder is a very important component in the design of application specific integrated circuits. In this paper, authors propose three new 1-bit full adders having a delay of 2-transistor (2T) using existing XOR and XNOR gates. The power consumption, delay and area of these new full adders are compared with existing ones and the results appear to be promising. The combination of low power, low transistor count and lesser delay makes the new full adders a viable option for efficient design.
引用
收藏
页码：701 / 704
页数：4
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