Analog Performance of Gate-Source/Drain Underlap Triple-Gate SOI nMOSFET

被引：5

作者：

dos Santos, S. D. ^{[1
]}

Nicoletti, T. ^{[1
]}

Martino, J. A. ^{[1
]}

机构：

[1] Univ Sao Paulo, LSI PSI USP, BR-05508010 Sao Paulo, Brazil

来源：

MICROELECTRONICS TECHNOLOGY AND DEVICES - SBMICRO 2011 | 2011年 / 39卷 / 01期

关键词：

FINFET;

D O I：

10.1149/1.3615199

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

The electrical characteristics of triple-gate SOI nMOSFET with gate-source/drain underlap are studied in this paper, focusing on the main analog parameters through 3D numerical simulations. The use of underlap has been reported as one alternative to avoid short channel effects mainly in non-planar transistors. The results indicate that in spite of the underlapped devices show lower drain current (I-DS) and transconductance (gm), superior characteristics are achieved in terms of transistor efficiency (gm/I-DS ratio), output conductance (g(D)), Early voltage (V-EA) and intrinsic voltage gain (A(V)) which are required for analog applications.

引用

页码：239 / 246

页数：8

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