A Novel Method for Design and Implementation of Low Power, High Stable SRAM cell

被引：0

作者：

Sharma, Ashish Kumar ^{[1
]}

Ravi, V. ^{[1
]}

机构：

[1] VIT Univ, Sch Elect Engn, Madras, Tamil Nadu, India

来源：

2017 INTERNATIONAL CONFERENCE ON NEXTGEN ELECTRONIC TECHNOLOGIES: SILICON TO SOFTWARE (ICNETS2) | 2017年

关键词：

ICRIT; N-Curve; SNM (Static noise margin); WTI (Write trip current); ADM (Access disturb margin); FF (fast fast); FS (fast slow); SF (slow fast); SS (slow slow); TT (typical typical);

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

SRAM is widely used cache memory in the world. Materialization of low power SRAM with highest stability is a need of the hour. As from many years the requirement of fast and low power devices are augmenting. In this paper, in first part described about stability analysis from ADM (extract from N-Curve). After that information about leakage power is given. One 8T SRAM circuit is proposed with low power and highest probable stability. This paper promises reduction in power by 66%. The stability of the cell is also increased, i.e. WNM increased by 15.9%; penalty is in RNM by 7.9 %.

引用

页码：112 / 116

页数：5

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