Design of an Low Power Miller Compensated Two Stage OP-AMP using 45 nm Technology for High Data Rate Communication

被引：0

作者：

Sarma, Manash Pratim ^{[1
]}

Kalita, Nilotpal

Mastorakis, Nikos E. ^{[2
]}

机构：

[1] Gauhati Univ, Dept Elect & Commun Engn, Gauhati, Assam, India

[2] Tech Univ Sofia, English Language Fac Engn, Sofia, Bulgaria

来源：

2017 4TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) | 2017年

关键词：

Miller Compensation; Unity Gain RW; Phase Margin; LOW-VOLTAGE;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper reports a new design of a low power two stage operational amplifier with Miller compensated topology for enhancing stability. The circuit is designed and simulated in Tanner EDA tool using 45 nm. CMOS technology. A significant reduction in power and enhancement of unity gain BW is achieved with a satisfactory phase margin. Several parameters are computed and compared with a few contemporary works to establish the efficacy of the design.

引用

页码：463 / 467

页数：5

共 50 条

[21] Implementation of High-Gain Low-Power Two Stage CMOS OP-AMP Employing Current Buffer Compensation in Nanoscale Regime
Gupta, Pragati
Akashe, Shyam
JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2021, 16 (01): : 51 - 59
[22] An ultra-high gain low power two stage CMOS op-amp based on inverse aspect ratio self cascode structures
Vajpayee, Prateek
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2014, 81 (02) : 349 - 359
[23] An ultra-high gain low power two stage CMOS op-amp based on inverse aspect ratio self cascode structures
Prateek Vajpayee
Analog Integrated Circuits and Signal Processing, 2014, 81 : 349 - 359
[24] Design & Implementation of High Speed and Low Power PLL Using GPDK 45 nm Technology
Badiger N.A.
Iyer S.
Journal of The Institution of Engineers (India): Series B, 2024, 105 (02) : 239 - 249
[25] Application of Improved PSO for Optimal Design of CMOS Two-stage Op-amp using Nulling Resistor Compensation Circuit
De, Bishnu Prasad
Maji, K. B.
Kar, R.
Mandal, D.
Ghoshal, S. P.
PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON 2017 DEVICES FOR INTEGRATED CIRCUIT (DEVIC), 2017, : 110 - 115
[26] A low-power, high-speed, current-feedback op-amp with a novel class AB high current output stage
Bales, J
PROCEEDINGS OF THE 1996 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 1996, : 101 - 104
[27] A low-power, high-speed, current-feedback op-amp with a novel class AB high current output stage
Bales, J
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (09) : 1470 - 1474
[28] A low-power sigma-delta modulator based on high-order op-amp sharing technique for speech communication
Dong, Siwan
Ning, Sihao
Yuan, Menghan
Wang, Peng
Yang, Wenju
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2024, 176
[29] An Ultra-Low-Power Low-Voltage Two Stage CMOS Operational Amplifier in 45 nm Technology
Gupta, Pragati
Khandelwal, Saurabh
Akashe, Shyam
JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2015, 10 (03) : 327 - 332
[30] Design of a low-power, high speed op-amp flair 10bit 300Msps parallel pipeline ADCs
Zhang, Sidong
Huang, Lu
Lin, Beiyuan
2007 IEEE INTERNATIONAL CONFERENCE ON INTEGRATION TECHNOLOGY, PROCEEDINGS, 2007, : 504 - +

← 1 2 3 4 5 →