Design of an Low Power Miller Compensated Two Stage OP-AMP using 45 nm Technology for High Data Rate Communication

被引：0

作者：

Sarma, Manash Pratim ^{[1
]}

Kalita, Nilotpal

Mastorakis, Nikos E. ^{[2
]}

机构：

[1] Gauhati Univ, Dept Elect & Commun Engn, Gauhati, Assam, India

[2] Tech Univ Sofia, English Language Fac Engn, Sofia, Bulgaria

来源：

2017 4TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) | 2017年

关键词：

Miller Compensation; Unity Gain RW; Phase Margin; LOW-VOLTAGE;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper reports a new design of a low power two stage operational amplifier with Miller compensated topology for enhancing stability. The circuit is designed and simulated in Tanner EDA tool using 45 nm. CMOS technology. A significant reduction in power and enhancement of unity gain BW is achieved with a satisfactory phase margin. Several parameters are computed and compared with a few contemporary works to establish the efficacy of the design.

引用

页码：463 / 467

页数：5

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