A new all-digital phase-locked loop with high precision and low jitter

被引：3

作者：

Chow, Hwang-Cherng ^{[1
]}

Su, Chung-Hsin ^{[1
]}

机构：

[1] Chang Gung Univ, Dept & Grad Inst Elect Engn, Tao Yuan, Taiwan

来源：

INTERNATIONAL JOURNAL OF ELECTRONICS | 2008年 / 95卷 / 12期

关键词：

all-digital phase-locked loop; digitally controlled oscillator; high precision; low jitter; delay element;

D O I：

10.1080/00207210802447827

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new method is proposed in this article to accomplish the fine tune unit of the digitally controlled oscillator of an all-digital phase-locked loop (ADPLL). Instead of using adjustable currents, we utilise the difference of the equivalent capacitance obtained from the drain of MOS transistors between on and off states as the fine tune delay parameter. Based on post-layout simulation results, the time resolution of the fine tune delay element can achieve results as good as 1.7126ps. The operating frequency of this presented ADPLL ranges from 308 to 587MHz. As compared to prior arts, the power consumption per MHz is reduced over 15% and the jitter is as low as 5ps, which is a significant improvement.

引用

页码：1241 / 1249

页数：9

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