A Novel Error Detection Strategy for a Low Power Low Noise All-Digital Phase-Locked Loop

In an all-digital phase-locked loop (ADPLL), time-to-digital converter (TDC) is a paramount block. Nevertheless, design issues and solutions to resolve them always increase the complexity of the system. A novel strategy to handle the frequency error detection in a type-II ADPLL architecture is analyzed in this work. This strategy has several advantages of scalability and integration and reduces complexity up to a greater extent than conventional AD-PLLs. Consequently, this strategy enhances its applicability in less stringent applications like PLL based frequency synthesizers. Mathematical analysis showing the advantages in choosing this strategy to detect the phase error is demonstrated. The theoretical and simulated phase noise analysis is also provided and compared with the conventional technique. The power consumption of the PLL using this proposed strategy is as low as 1.9 mW.