An area-efficient iterative modified-booth multiplier based on self-timed clocking

被引：4

作者：

Shin, MC ^{[1
]}

Kang, SH ^{[1
]}

Park, IC ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept EECS, Taejon 305701, South Korea

来源：

2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ICCD.2001.955079

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a multiplication. The partial CSA array is controlled by a fast internal clock generated using a self-timed technique. Compared with the array implementation, the proposed multiplier yields an 86.6% area reduction at the expense of 18.8% slow down for 64x64-bit multiplication.

引用

页码：511 / 512

页数：2