An area-efficient iterative modified-booth multiplier based on self-timed clocking

被引：4

作者：

Shin, MC ^{[1
]}

Kang, SH ^{[1
]}

Park, IC ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept EECS, Taejon 305701, South Korea

来源：

2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ICCD.2001.955079

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a multiplication. The partial CSA array is controlled by a fast internal clock generated using a self-timed technique. Compared with the array implementation, the proposed multiplier yields an 86.6% area reduction at the expense of 18.8% slow down for 64x64-bit multiplication.

引用

页码：511 / 512

页数：2

共 32 条

[11] A fast and power-saving self-timed Manchester carry-bypass adder for booth multiplier-accumulator design
Wey, IC
Chow, HC
Chen, YG
Wu, AY
PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, : 50 - 53
[12] Design of area-efficient modified decoder-based imprecise multiplier for error-resilient applications
Anguraj, Parthibaraj
Krishnan, Thiruvenkadam
MICROELECTRONICS JOURNAL, 2023, 141
[13] An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA
Kim, Sunwoong
Rutenbar, Rob A.
GLSVLSI '19 - PROCEEDINGS OF THE 2019 ON GREAT LAKES SYMPOSIUM ON VLSI, 2019, : 87 - 92
[14] Area-efficient and self-biased capacitor multiplier for on-chip loop filter
Hwang, I. -C.
ELECTRONICS LETTERS, 2006, 42 (24) : 1392 - 1394
[15] Area Efficient Modified Booth Adder based on Sklansky Adder
Garg, Anubhav
Agrawal, Deepak
Kularia, Priyank
Gaur, Nidhi
Mehra, Anu
Rajput, Sachin
2017 2ND INTERNATIONAL CONFERENCE FOR CONVERGENCE IN TECHNOLOGY (I2CT), 2017, : 308 - 312
[16] High-Speed and Area-Efficient LUT-Based BCD Multiplier Design
Sworna, Zarrin Tasnim
Ul Haque, Mubin
Anisuzzaman, D. M.
2018 4TH IEEE INTERNATIONAL WIE CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (IEEE WIECON-ECE 2018), 2018, : 33 - 36
[17] AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography
Hu, Xiao
Tian, Jing
Li, Minghao
Wang, Zhongfeng
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 70 (02) : 719 - 732
[18] High-speed, area-efficient FPGA-based floating-point multiplier
Aty, GA
Hussein, AI
Ashour, IS
Mones, M
ICM 2003: PROCEEDINGS OF THE 15TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2003, : 274 - 277
[19] Ultra Low-Power, Area-Efficient Multiplier Based on Shift-and-Add Architecture
Javanmardi, Karwan
Amini, Abdollah
Cabrini, Alessandro
2022 29TH INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM (MIXDES 2022), 2022, : 120 - 123
[20] Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure
Acosta, AJ
Jimenez, R
Barriga, A
Bellido, MJ
Valencia, M
Huertas, JL
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1998, 145 (04): : 247 - 253

← 1 2 3 4 →