An area-efficient iterative modified-booth multiplier based on self-timed clocking

被引：4

作者：

Shin, MC ^{[1
]}

Kang, SH ^{[1
]}

Park, IC ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept EECS, Taejon 305701, South Korea

来源：

2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ICCD.2001.955079

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a multiplication. The partial CSA array is controlled by a fast internal clock generated using a self-timed technique. Compared with the array implementation, the proposed multiplier yields an 86.6% area reduction at the expense of 18.8% slow down for 64x64-bit multiplication.

引用

页码：511 / 512

页数：2

共 32 条

[21] High Speed, Efficient Area, Low Power Novel Modified Booth Encoder Multiplier for Signed-Unsigned Number
Rajput, Ravindra P.
Swamy, M. N. Shanmukha
ARTIFICIAL INTELLIGENCE PERSPECTIVES IN INTELLIGENT SYSTEMS, VOL 1, 2016, 464 : 321 - 333
[22] Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style
Pan, Wanyuan
Yu, Yihe
Tang, Chengcheng
Yin, Ningyuan
Yu, Zhiyi
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2024, 71 (07) : 3538 - 3542
[23] A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline
Trudeau, L. -C.
Gagnon, G.
Gagnon, F.
Thibeault, C.
Awad, T.
Morrissey, D.
21ST IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC 2015), 2015, : 17 - 18
[24] An area-efficient memory-based multiplier powering eight parallel multiplications for convolutional neural network processors
Choi, Seongrim
Cho, Suhwan
Nam, Byeong-Gyu
ELECTRONICS LETTERS, 2021, 57 (15) : 573 - 575
[25] A modified prefix operator well suited for area-efficient brick-based adder implementations
Rust, I
Noll, T. G.
ADVANCES IN RADIO SCIENCE, 2011, 9 : 289 - 295
[26] Low-Power and Area-Efficient Finite Field Multiplier Architecture Based on Irreducible All-One Polynomials
Mohaghegh, Shima
Yemiscioglu, Gurtac
Muhtaroglu, Ali
2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,
[27] High-Throughput and Area-Efficient MIMO Symbol Detection Based on Modified Dijkstra's Search
Kim, Tae-Hwan
Park, In-Cheol
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (07) : 1756 - 1766
[28] Implementation of a High-throughput and Area-efficient MIMO Detector Based on Modified Dijkstra's Search
Kim, Tae-Hwan
Park, In-Cheol
GLOBECOM 2009 - 2009 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, VOLS 1-8, 2009, : 2218 - 2223
[29] Area-Efficient Binarized Neural Network Inference Accelerator Based on Time-Multiplexed XNOR Multiplier Using Loadless 4T SRAM
Zhu, Yihan
Ohsawa, Takashi
IEICE TRANSACTIONS ON ELECTRONICS, 2024, E107C (12) : 545 - 556
[30] Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array
Kuo, Chao-Tsung
Wu, Yao-Cheng
ELECTRONICS, 2024, 13 (02)

← 1 2 3 4 →