Design of adiabatic two's complement multiplier-accumulator based on CTGAL

被引：2

作者：

Wang, Peng-jun ^{[1
]}

Xu, Jian ^{[1
]}

Ying, Shi-yan ^{[2
]}

机构：

[1] Ningbo Univ, Inst Circuits & Syst, Ningbo 315211, Peoples R China

[2] Zhejiang Univ Technol, Coll Informat Engn, Hangzhou 310014, Zhejiang, Peoples R China

来源：

JOURNAL OF ZHEJIANG UNIVERSITY-SCIENCE A | 2009年 / 10卷 / 02期

基金：

中国国家自然科学基金;

关键词：

CTGAL circuit; Adiabatic circuit; Booth arithmetic; Multiplier; Two's complement MAC;

D O I：

10.1631/jzus.A0820013

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic (CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two's complement multiplier-accumulator (MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor (CMOS) logic.

引用

页码：172 / 178

页数：7

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