A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-test

被引:0
|
作者
Fukazawa, Yuki [1 ]
Iwagaki, Tsuyoshi [1 ]
Ichihara, Hideyuki [1 ]
Inoue, Tomoo [1 ]
机构
[1] Hiroshima City Univ, Grad Sch Informat Sci, Asaminami Ku, Hiroshima 7313194, Japan
关键词
Fault tolerance; test pattern generators; test-reliability; cyclic code; on-line BIST; real-time application; YIELD;
D O I
10.1109/ATS.2013.24
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Reliable built-in self-test (Reliable BIST) is a scheme in which embedded circuits used for self-testing circuits-under-test (CUTs) are designed to be tolerant of their faults. Reliable BIST is especially important for highly reliable on-line testing for real-time system; reliable BIST is required to recover itself from transient errors of its embedded BIST circuits. In this paper, we propose a transient fault tolerant test pattern generator (TPG) for a reliable BIST scheme. The proposed TPG, called EC-TPG, can correct (or mask) errors that occur on itself during testing CUTs, so that it can enhance its test-reliability, which is the probability that the TPG can generate correct (expected) test patterns. We analyze the test-reliability of EC-TPG in order to show that EC-TPG has high test-reliability. Furthermore we demonstrate that, in on-line BIST for real-time systems, EC-TPG can achieve higher test-reliability compared with a test re-execution scheme with error detection through some case studies.
引用
收藏
页码:85 / 90
页数:6
相关论文
共 50 条
  • [31] Synthesis for arithmetic built-in self-test
    Stroele, Albrecht P.
    Proceedings of the IEEE VLSI Test Symposium, 2000, : 165 - 170
  • [32] Accumulator-based built-in self-test generator for robustly detectable sequential fault testing
    Voyiatzis, I
    Kranitis, N
    Gizopoulos, D
    Paschalis, A
    Halatsis, C
    IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2004, 151 (06): : 466 - 472
  • [33] Testing and built-in self-test - A survey
    Steininger, A
    JOURNAL OF SYSTEMS ARCHITECTURE, 2000, 46 (09) : 721 - 747
  • [34] BUILT-IN SELF-TEST OF A CMOS ALU
    CERNY, E
    ABOULHAMID, M
    BOIS, G
    CLOUTIER, J
    IEEE DESIGN & TEST OF COMPUTERS, 1988, 5 (04): : 38 - 48
  • [35] Built-in self-test for signal integrity
    Nourani, M
    Attarha, A
    38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001, 2001, : 792 - 797
  • [36] BUILT-IN SELF-TEST OF DIGITAL DECIMATORS
    ADHAM, S
    KASSAB, M
    RAJSKI, J
    TYSZER, J
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1995, 42 (07): : 486 - 492
  • [37] Programmable deterministic Built-In Self-Test
    Hakmi, Abdul-Wahid
    Wunderlich, Hans-Joachim
    Zoellin, Christian G.
    Glowatz, Andreas
    Hapke, Friedrich
    Schloeffel, Juergen
    Souef, Laurent
    2007 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, 2007, : 476 - +
  • [38] Asynchronous Interleaved Scan Architecture for On-line Built-in Self-test of Null Convention Logic
    Nemati, Nastaran
    Reed, Mark C.
    Fant, Karl
    Beckett, Paul
    2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 746 - 749
  • [39] Built-in self-test of FPGA interconnect
    Stroud, C
    Wijesuriya, S
    Hamilton, C
    Abramovici, M
    INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS, 1998, : 404 - 411
  • [40] Built-in self-test with an alternating output
    Bogue, T
    Gossel, M
    Jurgensen, H
    Zorian, Y
    DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS, 1998, : 180 - 184