Investigations of using NMOS parasitic bipolar transistor for ESD protection circuits

被引：0
|
作者：
Suzuki, Teruo [1 ]
机构：
[1] Socionext Inc, 2-1844-2 Kozoji Cho, Kasugai, Aichi 4870013, Japan
来源：
2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2018年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Electro-Static Discharge (ESD) protection circuit by parasitic lateral NPN bipolar transistors (LNPN) is used especially for NMOS Open Drain structure for signal Input/Output (IO) cell like Inter-Integrated Circuit (I2C) or Fail Safe IO. In power clamp, the LNPN is effective for very fast power ramp up case to avoid inrush current. In this paper, studies of good point and bad point are presented regarding the LNPN.
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收藏
页码：733 / 736
页数：4
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