共 50 条
- [1] Thermal-Aware Floorplanning for 3D MPSoCs IEEE DESIGN & TEST OF COMPUTERS, 2011, 28 (02): : 78 - 78
- [2] Thermal-aware incremental floorplanning for 3D ICs ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 1092 - 1095
- [3] Interconnect and thermal-aware floorplanning for 3D microprocessors ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2006, : 98 - +
- [4] Fixed-outline Thermal-aware 3D Floorplanning 2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, : 552 - +
- [5] The Thermal-aware Floorplanning for 3D ICs using carbon nanotube PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS), 2010, : 1155 - 1158
- [6] Thermal-aware Floorplanning Guidelines for 3D ICs with Integrated Microchannels PROCEEDINGS OF THE 25TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM (MIXDES 2018), 2018, : 258 - 261
- [7] Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2009, E92A (12): : 2979 - 2989
- [8] Boosting the 3D thermal-aware floorplanning problem through a master-worker parallel MOEA CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2013, 25 (08): : 1089 - 1103