High level test generation for custom hardware: An industrial perspective

被引:0
|
作者
Ghosh, I [1 ]
机构
[1] Fujitsu Labs Amer, Sunnyvale, CA 94085 USA
来源
14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS | 2005年
关键词
RTL; ATPG; testing; validation; fault-coverage; fault simulation; functional test;
D O I
10.1109/ATS.2005.65
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:458 / 458
页数:1
相关论文
共 50 条
  • [31] Automatic Generation of Custom SIMD Instructions for Superword Level Parallelism
    Kim, Taemin
    Hoskote, Yatin
    2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE), 2014,
  • [32] Custom Test Chip for System-level ESD Investigations
    Thomson, Nicholas
    Xiu, Yang
    Mertens, Robert
    Keel, Min-Sun
    Rosenbaum, Elyse
    2014 36TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2014,
  • [33] Synthesizable High Level Hardware Descriptions
    Gillenwater, Jennifer
    Malecha, Gregory
    Salama, Cherif
    Zhu, Angela Yun
    Taha, Walid
    Grundy, Jim
    O'leary, John
    NEW GENERATION COMPUTING, 2010, 28 (04) : 339 - 369
  • [34] Synthesizable High Level Hardware Descriptions
    Jennifer Gillenwater
    Gregory Malecha
    Cherif Salama
    Angela Yun Zhu
    Walid Taha
    Jim Grundy
    John O’leary
    New Generation Computing, 2010, 28 : 339 - 369
  • [35] High-level test generation from VHDL behavioral descriptions
    Gharebaghi, AM
    Navabi, Z
    VHDL INTERNATIONAL USERS FORUM FALL WORKSHOP, PROCEEDINGS, 2000, : 123 - 126
  • [36] Synthesis of high-level requirements models for automatic test generation
    Gupta, P
    Cunning, SJ
    Rozenblit, JW
    EIGHTH ANNUAL IEEE INTERNATIONAL CONFERENCE AND WORKSHOP ON THE ENGINEERING OF COMPUTER BASED SYSTEMS, PROCEEDINGS, 2001, : 76 - 82
  • [37] Automatic generation of digital twin industrial system from a high level specification
    Campos, Julio Garrido
    Lopez, Juan Saez
    Quiroga, Jose Ignacio Armesto
    Seoane, Angel Manuel Espada
    29TH INTERNATIONAL CONFERENCE ON FLEXIBLE AUTOMATION AND INTELLIGENT MANUFACTURING (FAIM 2019): BEYOND INDUSTRY 4.0: INDUSTRIAL ADVANCES, ENGINEERING EDUCATION AND INTELLIGENT MANUFACTURING, 2019, 38 : 1095 - 1102
  • [38] Systematic Test Generation for Secure Hardware Supported Virtualization
    Kan, Senwen
    Dworak, Jennifer
    2017 IEEE 15TH INTL CONF ON DEPENDABLE, AUTONOMIC AND SECURE COMPUTING, 15TH INTL CONF ON PERVASIVE INTELLIGENCE AND COMPUTING, 3RD INTL CONF ON BIG DATA INTELLIGENCE AND COMPUTING AND CYBER SCIENCE AND TECHNOLOGY CONGRESS(DASC/PICOM/DATACOM/CYBERSCI, 2017, : 550 - 556
  • [39] Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs
    Jerbi, Khaled
    Raulet, Mickael
    Deforges, Olivier
    Abid, Mohamed
    VLSI DESIGN, 2012, Hindawi Limited (2012)
  • [40] AUTOMATIC GENERATION OF SYNTHESIZABLE HARDWARE IMPLEMENTATION FROM HIGH LEVEL RVC-CAL DESCRIPTION
    Jerbi, Khaled
    Raulet, Mickael
    Deforges, Olivier
    Abid, Mohamed
    2012 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP), 2012, : 1597 - 1600