An ASIC Design of a High-Speed Clock and Data Recovery Circuit

被引：0

作者：

Ng, Chi-Wai ^{[1
]}

Yu, Kai-Hung ^{[2
]}

Sham, Chiu-Wing ^{[1
]}

Tse, C. K. Michael ^{[1
]}

机构：

[1] Hong Kong Polytech Univ, Hong Kong, Hong Kong, Peoples R China

[2] IC Dev Ctr, Shatin, Peoples R China

来源：

MEMS, NANO AND SMART SYSTEMS, PTS 1-6 | 2012年 / 403-408卷

关键词：

Clock and Data Recovery; Phase Lock Loop; Voltage Control Oscillator;

D O I：

10.4028/www.scientific.net/AMR.403-408.1218

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Clock and Data Recovery (CDR) means that the digital data streams are sent without an accompanying clock signal. A digital CDR circuit is proposed as it does not depend on the special analog process and provide higher immunity to the noise. This design is fabricated using 0.13 mu m standard process and the circuit can support up to 5 GHz data rate to support the high speed standard. Compared to other CDR design with more advanced technology, our implementation can have similar performance but the manufacturing cost can be reduced.

引用

页码：1218 / +

页数：3

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