Electrical characterization of high-k gate dielectrics on semiconductors

被引：0
|
作者：
Ma, T. P. [1 ]
机构：
[1] Yale Univ, Dept Elect Engn, New Haven, CT 06520 USA
来源：
APPLIED SURFACE SCIENCE | 2008年 / 255卷 / 03期
基金：
美国国家科学基金会;
关键词：
Electrical characterization; High-k dielectrics; Semiconductors; MOSFET; IETS; Charge pumping; Lateral profiling;
D O I：
10.1016/j.apsusc.2008.07.010
中图分类号：
O64 [物理化学（理论化学）、化学物理学];
学科分类号：
070304 ; 081704 ;
摘要：
This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks: ( 1) inelastic electron tunneling spectroscopy (IETS), ( 2) lateral pro. ling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, and ( 3) pulse agitated substrate hot electron injection (PASHEI) technique for measuring trapping effects in the gate dielectric at low and modest gate voltages. (c) 2008 Elsevier B. V. All rights reserved.
引用
收藏
页码：672 / 675
页数：4
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