Time-multiplexed System-on-Chip using Fault-tolerant Astrocyte-Neuron Networks

Spike-based brain-inspired systems have shown an immense capability to achieve internal stability, widely referred to as homeostasis. This ability enrols them as the best candidate for next-generation computational neuroscience as they bridge the gap between neuroscience and machine learning. Spiking Neural Networks (SNN), a third generation Artificial Neural Network (ANN), which operates using discrete events of spikes, contributes to a category of biologically-realistic models of neurons to carry out computations. Spiking Astrocyte-Neuron Networks (SANN) have a characteristic attribute homologous to brain self-repair. Although SNNs are more powerful in theory than 2nd generation ANNs, they are not widely in use as their implementations on normal hardware are computationally-intensive. On the contrary, due to the capability of modern hardware such as FPGAs, which operates in MHz and GIIs range, facilitates real-time and faster-than-real-time simulations of SNNs. In this work, we overcome the computational overhead of the SNNs using the benefits of real-time hardware computations, utilizing time-multiplexing to design a Self-rePairing spiking Astrocyte Neural NEtwoRk (SPANNER) chip, generic to users' choice of task, emphasizing fault-tolerance, targeting safety-critical applications. We demonstrate the proposed methodology on a SANN system implemented on Xilinx Artix-7 FPGA. The proposed architecture has minimal hardware footprints, power dissipation profile and real-time computational capability, enhancing its usability in constrained applications.