Response to comments to "A distributive-transconductance model for border traps in IIIAV/High-k MOS capacitors"

被引：0
|
作者：
Zhang, Chen [1 ]
Xu, Min [1 ]
Ye, Peide D. [2 ]
Li, Xiuling [1 ]
机构：
[1] Univ Illinois, Elect & Comp Engn Dept, Urbana, IL 61822 USA
[2] Purdue Univ, Dept Elect & Comp Engn, W Lafayette, IN 47907 USA
来源：
IEEE ELECTRON DEVICE LETTERS | 2013年 / 34卷 / 11期
关键词：
Transconductance; Electron traps; Semiconductor device modeling; High K dielectric materials; MOS capacitors; Numerical models; Capacitance;
D O I：
10.1109/LED.2013.2282234
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：1441 / 1441
页数：1
相关论文
共 50 条
  • [31] PHYSICAL MODELING OF ELECTRICAL AND DIELECTRIC PROPERTIES OF HIGH-k Ta2O5 BASED MOS CAPACITORS ON SILICON
    Novkovski, Nenad
    FACTA UNIVERSITATIS-SERIES ELECTRONICS AND ENERGETICS, 2014, 27 (02) : 259 - 273
  • [32] On MOS admittance modeling to study border trap capture/emission and its effect on electrical behavior of high-k/III-V MOS devices
    Vais, Abhitosh
    Martens, Koen
    Lin, Dennis
    Collaert, Nadine
    Mocuta, Anda
    DeMeyer, Kristin
    Thean, Aaron
    MICROELECTRONIC ENGINEERING, 2015, 147 : 227 - 230
  • [33] Germanium surface passivation and atomic layer deposition of high-k dielectrics-a tutorial review on Ge-based MOS capacitors
    Xie, Qi
    Deng, Shaoren
    Schaekers, Marc
    Lin, Dennis
    Caymax, Matty
    Delabie, Annelies
    Qu, Xin-Ping
    Jiang, Yu-Long
    Deduytsche, Davy
    Detavernier, Christophe
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2012, 27 (07)
  • [34] Role of Hetero Interface of Ionic/Covalent Oxides for Pt/High-k/SiO2/Si MOS Capacitors on Vfb Shift
    Nabatame, Toshihide
    Ohi, Akihiko
    Chikyow, Toyohiro
    PHYSICS AND TECHNOLOGY OF HIGH-K MATERIALS 8, 2010, 33 (03): : 59 - 66
  • [35] Pretreatment Effects on High-k/InxGa1-xAs MOS Interface Properties and Their Physical Model
    Yokoyama, Chiaki
    Chang, Chi-Yu
    Takenaka, Mitsuru
    Takagi, Shinichi
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2018, 6 (01): : 487 - 493
  • [36] Effect of high-K dielectric on differential conductance and transconductance of ID-DG MOSFET following Ortiz-Conde model
    Deyasi, Arpan
    Sarkar, Angsuman
    Roy, Krishnendu
    Chowdhury, Anal Roy
    MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2021, 27 (11): : 3967 - 3975
  • [37] Effect of high-K dielectric on differential conductance and transconductance of ID-DG MOSFET following Ortiz-Conde model
    Arpan Deyasi
    Angsuman Sarkar
    Krishnendu Roy
    Anal Roy Chowdhury
    Microsystem Technologies, 2021, 27 : 3967 - 3975
  • [38] Effect of high-pressure deuterium annealing with high-K stack onto In0.53Ga0.47As MOS capacitors on 300 mm Si substrate
    Shin, Seung Heon
    Kim, Dae-Hyun
    Kim, Tae-Woo
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2018, 57 (11)
  • [39] Relationship between effective mobility and border traps associated with charge trapping in In0.7Ga0.3As MOSFETs with various high-k stacks
    Kwon, Hyuk-Min
    Kim, Dae-Hyun
    Kim, Tae-Woo
    APPLIED PHYSICS EXPRESS, 2018, 11 (03)
  • [40] An improved physically based compact c-v model for mos devices with HIGH-K gate dielectrics
    Bin Shams, Md. Itrat
    Habib, K. M. Masum
    Mikaill, Rajib
    Khosru, Quazi Deen Mohd
    Zainuddin, A. N. M.
    Haque, A.
    ICECE 2006: PROCEEDINGS OF THE 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, 2006, : 518 - +
12345