On MOS admittance modeling to study border trap capture/emission and its effect on electrical behavior of high-k/III-V MOS devices

被引：6

作者：

Vais, Abhitosh ^{[1
,2
]}

Martens, Koen ^{[1
]}

Lin, Dennis ^{[1
]}

Collaert, Nadine ^{[1
]}

Mocuta, Anda ^{[1
]}

DeMeyer, Kristin ^{[1
,2
]}

Thean, Aaron ^{[1
]}

机构：

[1] IMEC, B-3001 Leuven, Belgium

[2] Katholieke Univ Leuven, Dept Elect Engn, B-3001 Leuven, Belgium

来源：

MICROELECTRONIC ENGINEERING | 2015年 / 147卷

关键词：

MOS; III-V; Admittance model; Capacitance; Frequency dispersion; Border traps;

D O I：

10.1016/j.mee.2015.04.087

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present results of a study on border trap capture/emission (C/E) process and its effect on small signal admittance of III-V devices. A MOS admittance model using a non-radiative multi-phonon phenomenon as the basis of the border trap capture/emission process is developed and utilized to investigate the effect of parameters like temperature, gate voltage, oxide thickness and trap distribution on capture/emission process. The simulation results are found to match closely with experimentally observed temperature, voltage and dielectric thickness dependencies in experimental admittance data. (C) 2015 Elsevier B.V. All rights reserved.

引用

页码：227 / 230

页数：4

共 15 条

[1] An Analytical Model of MOS Admittance for Border Trap Density Extraction in High-k Dielectrics of III-V MOS Devices
Vais, Abhitosh
Martens, Koen
Lin, Dennis
Mocuta, Anda
Collaert, Nadine
Thean, Aaron
DeMeyer, Kristin
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (12) : 4707 - 4713
[2] A Distributive-Transconductance Model for Border Traps in III-V/High-k MOS Capacitors
Zhang, Chen
Xu, Min
Ye, Peide D.
Li, Xiuling
IEEE ELECTRON DEVICE LETTERS, 2013, 34 (06) : 735 - 737
[3] The Relationship between Border Traps characterized by AC Admittance and BTI in III-V MOS devices
Vais, A.
Martens, K.
Franco, J.
Lin, D.
Alian, A.
Roussel, P.
Sioncke, S.
Collaert, N.
Thean, A.
Heyns, M.
Groeseneken, G.
DeMeyer, Kristin
2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2015,
[4] Comments to "A Distributive-Transconductance Model for Border Traps in III-V/High-k MOS Capacitors"
Taur, Yuan
Chen, Han-Ping
Yuan, Yu
Yu, Bo
IEEE ELECTRON DEVICE LETTERS, 2013, 34 (10) : 1343 - 1344
[5] Reliability Study of MOS Devices by Profiling Trap Distribution in High-k Gate Dielectric
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Chang-Liao, Kuei-Shu
Tsao, Che-Hao
Ko, Hsueh-Chao
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[6] A new method for extracting interface state and border trap densities in high-k/III-V MOSFETs
Sereni, G.
Vandelli, L.
Larcher, L.
Morassi, L.
Veksler, D.
Bersuker, G.
2014 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2014,
[7] Charge trapping effects on Metal-Gate/High-k/III-V MOS devices assessed through C-V hysteresis
Pazos, Sebastian M.
Aguirre, Fernando L.
Palumbo, Felix
2017 ARGENTINE CONFERENCE OF MICRO-NANOELECTRONICS, TECHNOLOGY AND APPLICATIONS (CAMTA), 2017, : 21 - 25
[8] A New Quality Metric for III-V/High-k MOS Gate Stacks Based on the Frequency Dispersion of Accumulation Capacitance and the CET
Vais, Abhitosh
Franco, Jacopo
Martens, Koen
Lin, Dennis
Sioncke, Sonja
Putcha, Vamsi
Nyns, Laura
Maes, Jan
Xie, Qi
Givens, Michael
Tang, Fu
Jiang, Xiaoqiang
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IEEE ELECTRON DEVICE LETTERS, 2017, 38 (03) : 318 - 321
[9] Investigation of voltage-swing effect and trap generation in high-k gate dielectric of MOS devices by charge-pumping measurement
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Chang-Liao, Kuei-Shu
Lu, Chun-Chang
Tsai, Ping-Hung
Kyi, Yin Yin
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MICROELECTRONIC ENGINEERING, 2008, 85 (01) : 20 - 26
[10] Direct Extraction of Interface Trap States from the Low Frequency Gate C-V Characteristics of MOS Devices with Ultrathin High-K Gate Dielectrics
Satter, Md. M.
Haque, A.
PROCEEDINGS OF ICECE 2008, VOLS 1 AND 2, 2008, : 158 - +

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