Critical pattern selection method for full-chip source and mask optimization

被引:19
|
作者
Liao, Lufeng [1 ,2 ]
Li, Sikun [1 ,2 ]
Wang, Xiangzhao [1 ,2 ]
Zhang, Libin [2 ,3 ]
Gao, Pengzheng [2 ,3 ]
Wei, Yayi [2 ,3 ]
Shi, Weijie [4 ]
机构
[1] Chinese Acad Sci, Shanghai Inst Opt & Fine Mech, Lab Informat Opt & Optoelect Technol, Shanghai 201800, Peoples R China
[2] Univ Chinese Acad Sci, Ctr Mat Sci & Optoelect Engn, Beijing 100049, Peoples R China
[3] Chinese Acad Sci, Integrated Circuit Adv Proc Ctr, Inst Microelect, Beijing 100029, Peoples R China
[4] Dongfang Jingyuan Electron Ltd, Beijing 100176, Peoples R China
来源
OPTICS EXPRESS | 2020年 / 28卷 / 14期
基金
上海市自然科学基金;
关键词
EFFICIENT SOURCE;
D O I
10.1364/OE.396362
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
Source and mask optimization (SMO) is one of the most important resolution enhancement techniques for integrated circuit manufacturing in 2X nm technology node and beyond. Nowadays full-chip SMO is alternatively realized by applying SMO to limited number of selected critical patterns instead of to full-chip area, since it is too computational expensive to be apply SMO in full-chip area directly. The critical patterns are selected by a pattern selection method which enables SMO in full-chip application by balancing the performance and computation consumption. A novel diffraction-based pattern selection method has been proposed in this paper. In this method, diffraction-signatures are sufficiently described with widths in eight selected directions. Coverage rules between the diffraction-signatures are specifically designed. Diffraction-signature grouping method and pattern selection strategy are proposed based on the diffraction-signatures and coverage rules. A series of simulations and comparisons performed using ASML's Tachyon software, which is one of the state of the art commercial SMO platforms, verify the validity of the proposed method. (C) 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
引用
收藏
页码:20748 / 20763
页数:16
相关论文
共 50 条
  • [21] Enhancing mask synthesis for curvilinear masks in full-chip extreme ultraviolet lithography
    Hooker, Kevin
    Xiao, Guangming
    Tang, Yu-Po
    Zhang, Yunqiang
    Jeong, Moongyu
    Valadez, John
    Lucas, Kevin
    JOURNAL OF MICRO-NANOPATTERNING MATERIALS AND METROLOGY-JM3, 2023, 22 (04):
  • [22] Full-chip OPC and verification with a fast mask 3D model
    Huang, Hsu-Ting
    Mokhberi, Ali
    Dai, Huixiong
    Ngai, Chris
    OPTICAL MICROLITHOGRAPHY XXIV, 2011, 7973
  • [23] Full-chip analysis method of ESD protection network
    Hayashi, S
    Minami, F
    Yamada, M
    ISQED 2004: 5TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2004, : 439 - 444
  • [24] A Fast Full-Chip Static Power Estimation Method
    Wan, Jiachun
    Wang, Hai
    Tan, Sheldon X. -D.
    Zhang, Chi
    Yuan, Yuan
    Huang, Keheng
    Zhang, Zhenghong
    2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2016, : 241 - 243
  • [26] Full-chip based sub resolution assist features correction for mask manufacturing
    Bang, Ju-Mi
    Masumoto, Issei
    Ji, Min-Kyu
    Jang, Sung-Hoon
    Aburatani, Isao
    Choi, Ji-Hyun
    Woo, Sang-Gyun
    Cho, Han-Ku
    PHOTOMASK TECHNOLOGY 2007, PTS 1-3, 2007, 6730
  • [27] High accuracy OPC electromagnetic full-chip modeling for curvilinear mask OPC and ILT
    Sakr, Enas
    Levinson, Zac
    DeLancey, Rob
    Lee, C. Jay
    Li, Jinguang
    Chen, Ryan
    Iwanow, Robert
    Yang, Delian
    Hoppe, Wolfgang
    Latinwo, Folarin
    Lucas, Kevin
    Liu, Peng
    DTCO AND COMPUTATIONAL PATTERNING III, 2024, 12954
  • [28] Approach to full-chip simulation and correction of stencil mask distortion for proximity electron lithography
    Sawamura, J
    Suzuki, K
    Omori, S
    Ashida, I
    Ohnuma, H
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2004, 22 (06): : 3092 - 3096
  • [29] Fast 3D thick mask model for full-chip EUVL simulations
    Liu, Peng
    Xie, Xiaobo
    Liu, Wei
    Gronlund, Keith
    EXTREME ULTRAVIOLET (EUV) LITHOGRAPHY IV, 2013, 8679
  • [30] Full-chip simulation of LSI lithography mask using multi-scale analysis
    Sawamura, J.
    Suzuki, K.
    Ohtsubo, H.
    COMPUTATIONAL METHODS, PTS 1 AND 2, 2006, : 1641 - +