Ultralow Specific On-Resistance Superjunction Vertical DMOS With High-K Dielectric Pillar

被引:41
|
作者
Luo, Xiaorong [1 ,2 ]
Jiang, Y. H. [1 ]
Zhou, K. [1 ]
Wang, P. [1 ]
Wang, X. W. [1 ]
Wang, Q. [1 ]
Yao, G. L. [1 ]
Zhang, B. [1 ]
Li, Z. J. [1 ]
机构
[1] Univ Elect Sci & Technol China, State Key Lab Elect Thin Films & Integrated Devic, Chengdu 610054, Peoples R China
[2] China Elect Technol Grp Corp, Res Inst 24, Chongqing 400060, Peoples R China
基金
中国国家自然科学基金;
关键词
Breakdown voltage (BV); high relative permittivity; specific on-resistance; superjunction (SJ); SRTIO3; THIN-FILMS;
D O I
10.1109/LED.2012.2196969
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A superjunction (SJ) VDMOS with a high-k (HK) dielectric pillar below the trench gate is proposed and investigated by simulation. The HK dielectric causes a self-adapted assistant depletion of the n pillar. This not only increases the n-pillar doping concentration and thus reduces the specific on-resistance (R-on,R-sp) but also alleviates the charge-imbalance issue in SJ devices. The HK dielectric weakens the lateral field and enhances the vertical field strength in a high-voltage blocking state, leading to an improved breakdown voltage (BV). Ion implantation through trench sidewalls forms narrow and highly doped n pillars to further reduce the R-on,R-sp. The R-on,(sp) decreases by 42%, and BV increases by 15% compared with those of a conventional SJ VDMOS.
引用
收藏
页码:1042 / 1044
页数:3
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