A scalable parallel reconfigurable hardware architecture for DNA matching

被引:3
|
作者
Garcia Neto Segundo, Edgar Jose [1 ]
Nedjah, Nadia [1 ]
Mourelle, Luiza de Macedo [2 ]
机构
[1] Univ Estado Rio De Janeiro, Dept Elect Engn & Telecommun, Rio De Janeiro, Brazil
[2] Univ Estado Rio De Janeiro, Dept Syst Engn & Computat, Rio De Janeiro, Brazil
关键词
DNA alignment; DNA matching; Reconfigurable hardware; BLAST;
D O I
10.1016/j.vlsi.2013.01.002
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
DNA sequence matching is used in the identification of a relationship between a fragment of DNA and its owner by mean of a database of DNA registers. A DNA fragment could be a hair sample left at a crime scene by a suspect or provided by a person for a paternity exam. The process of aligning and matching DNA sequences is a computationally demanding process. In this paper, we propose a novel parallel hardware architecture for DNA matching based on the steps of the BLAST algorithm. The design is scalable so that its structure can be adjusted depending on the size of the subject and query DNA sequences. Moreover, the number of units used to perform in parallel can also be scaled depending some characteristics of the algorithm. The design was synthesized and programmed into FPGA. The trade-off between cost and performance were analyzed to evaluate different design configuration. (c) 2013 Elsevier B.V. All rights reserved.
引用
收藏
页码:240 / 246
页数:7
相关论文
共 50 条
  • [21] A new parallel hardware architecture for high-performance stereo matching calculation
    Seo, Young-Ho
    Yoo, Ji-Sang
    Kim, Dong-Wook
    INTEGRATION-THE VLSI JOURNAL, 2015, 51 : 81 - 91
  • [22] A Reconfigurable Hardware Architecture for Packet Processing
    Duan Tong
    Lan Julong
    Hu Yuxiang
    Liu Shiran
    CHINESE JOURNAL OF ELECTRONICS, 2018, 27 (02) : 428 - 432
  • [23] Research of parallel hardware architecture for matrix triangularization decomposition based on reconfigurable computing system
    Liu, Shu-Yong
    Wu, Yan-Xia
    Zhang, Bo-Wei
    Zhang, Guo-Yin
    Dai, Kui
    Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2015, 43 (08): : 1642 - 1650
  • [24] A Reconfigurable Hardware Architecture for Packet Processing
    DUAN Tong
    LAN Julong
    HU Yuxiang
    LIU Shiran
    Chinese Journal of Electronics, 2018, 27 (02) : 428 - 432
  • [25] Scalable run time reconfigurable architecture
    Touhafi, A
    Brissinck, W
    Dirkx, E
    VLSI: SYSTEMS ON A CHIP, 2000, 34 : 113 - 124
  • [26] A Reconfigurable and Scalable Architecture for Security Coprocessor
    Li, Chao
    Zhou, Jun
    Jiang, Yuan
    Chen, Canfeng
    Xu, Yongjun
    Luo, Zuying
    ICIEA 2010: PROCEEDINGS OF THE 5TH IEEE CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS, VOL 4, 2010, : 71 - +
  • [27] A scalable and reconfigurable WDM network architecture
    Guo, D
    Zhang, Z
    FIBER OPTIC COMPONENTS AND OPTICAL COMMUNICATIONS II, 1998, 3552 : 65 - 73
  • [28] ME64 - A highly scalable hardware parallel architecture motion estimation in FPGA
    Zandonai, D
    Bampi, S
    Bergerman, M
    16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS, 2003, : 93 - 98
  • [29] Hardware Parallel Architecture proposed to accelerate the Orthogonal Matching Pursuit Compressive Sensing Reconstruction
    Osorio Quero, C.
    Durini, D.
    Ramos-Garcia, R.
    Rangel-Magdaleno, J.
    Martinez-Carranza, J.
    COMPUTATIONAL IMAGING V, 2020, 11396
  • [30] Freely scalable and reconfigurable optical hardware for deep learning
    Bernstein, Liane
    Sludds, Alexander
    Hamerly, Ryan
    Sze, Vivienne
    Emer, Joel
    Englund, Dirk
    SCIENTIFIC REPORTS, 2021, 11 (01)