Impact of interface traps on performance of Gate-on-Source/Channel SOI TFET

Here, one of most important reliability issue of the semiconductor device, the effects of traps present at the oxide-semiconductor interfaces on gate-on-source/channel SOI TFET are investigated. Conventional SOI TFET, gate-on-source only TFET, and gate-on-source/channel TFET are compared and it is found that gate-on-source/channel TFET has better immunity to the interface trap charge variation. The gate-on-source/channel TFET exhibits higher on current and on-off current ratio than gate-on-source device. Preliminary analyses are presented for the proposed architecture for the parameters: gate-channel overlap, back gate voltage and buried oxide thickness in absence of interface traps. The back gate voltage has a significant effect on the channel-drain junction of the device, and hence, on the ambipolar current. Further, the device characteristics in presence of traps at the gate oxide-semiconductor interface and buried oxide-semiconductor interface are reported. The effect of trap concentration is observed on the transfer characteristics, capacitance, and cut off frequency. The front gate dielectric-semiconductor interface traps degrade on current, while the buried oxide-semiconductor interface traps affect the ambipolar current. The effect of back gate voltage on ambipolarity and on current of the proposed device is studied in detail in presence of traps.