Gauge control for sub 170 nm DRAM product features

被引:0
|
作者
Lafferty, N [1 ]
Gould, C [1 ]
Littau, M [1 ]
Raymond, CJ [1 ]
机构
[1] Rochester Inst Technol, Rochester, NY 14623 USA
关键词
D O I
10.1117/12.436754
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
As modern circuit architecture features steadily decrease in size, more accurate tools are needed to meaningfully measure critical dimensions (CD). As a general rule, a metrology tool should be able to measure 1/10 of the product tolerance. As CD's continue to shrink, gauge control becomes more relevant. The trend is illustrated in Table 1. Year 2000, 2001, 2002, 2004, Lithography Requirements similar to 175 nm, similar to 150 nm, similar to 130 nm, similar to 110 nm CD Tolerance 17.5 nm, 15 nm, 13 nm, 11 nm Gauge Control 1.8 nm, 1.5 nm, 1.3 nm, 1.1 nm Table 1. Lithographic Road Map(1) The standard in-line critical dimension measurement tool is the top-down scanning electron microscope (SEM). An emerging technology for high speed, high accuracy CD measurement is scatterometry. This paper will compare the two technologies for in-line CD measurement for three applications: A product etch step (assessing gauge capability as well as trending), a product resist step (trending), and lithographic cell monitors (trending).
引用
收藏
页码:454 / 461
页数:8
相关论文
共 50 条
  • [41] Improvement of performance and data retention characteristics of sub-50nm DRAM by HfSiON Gate dielectric
    Hyun, Sangjin
    Kim, Hye-Min
    Lee, Hye-Lan
    Nam, Kab-Jin
    Hong, Sug-Hun
    Kim, Dong-Chan
    Kim, Jihyun
    Jang, Soo-Ik
    Jeon, In Sang
    Kang, Sangbom
    Choi, Siyoung
    Chung, U-In
    Moon, Joo-Tae
    Ryu, Byung-Il
    2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 184 - +
  • [42] Investigation of Sub-20nm 4th generation DRAM cell transistor's parasitic resistance and scalable methodology for Sub-20nm era
    Jeong, Shinwoo
    Lee, Jin-Seong
    Jang, Jiuk
    Kim, Jooncheol
    Shin, Hyunsu
    Kim, Ji Hun
    Song, Jeongwoo
    Woo, Dongsoo
    Oh, Jeonghoon
    Lee, Jooyoung
    2023 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS, 2023,
  • [43] Picometre control for sub-70 nm geometries
    Semprez, Oliver
    2002, Angel Buiness Communications Ltd. (24):
  • [44] Extracting Opinionated (Sub) Features from a Stream of Product Reviews
    Zimmermann, Max
    Ntoutsi, Eirini
    Spiliopoulou, Myra
    DISCOVERY SCIENCE, 2013, 8140 : 340 - 355
  • [45] Sub 90nm DRAM Patterning by using modified chromeless PSM at KrF lithography era.
    Kim, YS
    Hyun, YS
    Kong, KK
    Kim, H
    Choi, BH
    Optical Microlithography XVIII, Pts 1-3, 2005, 5754 : 1388 - 1394
  • [46] Electrical characterization of sub-100nm features in semiconductor devices
    Liu, Lerwen
    2006 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2006, : A6 - A6
  • [47] Large-scale lithography for sub-500nm features
    Pelzer, R. L.
    Steininger, T.
    Belier, Benoit
    Julie, Gwenaelle
    INTERNATIONAL MEMS CONFERENCE 2006, 2006, 34 : 34 - 38
  • [48] Investigation of full-field CD control of sub-100 nm gate features by phase-shift 248-nm lithography
    Fritze, M
    Tyrrell, B
    Astolfi, D
    Davis, P
    Wheeler, B
    Mallen, R
    Jarmolowicz, J
    Cann, S
    Chan, D
    Rhyins, P
    Mastovich, M
    Sullivan, N
    Brandom, R
    Carney, C
    Ferri, J
    Blachowicz, BA
    METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XV, 2001, 4344 : 334 - 343
  • [49] Understanding the Competitive Interaction in Leakage Mechanisms for Effective Row Hammer Mitigation in Sub-20 nm DRAM
    Li, Jie
    Zhou, Longda
    Ye, Sheng
    Qiao, Zheng
    Ji, Zhigang
    IEEE ELECTRON DEVICE LETTERS, 2024, 45 (01) : 40 - 43
  • [50] Advancements and challenges of patterning biomolecules with sub-50 nm features
    Tran, Helen
    Killops, Kato L.
    Campos, Luis M.
    SOFT MATTER, 2013, 9 (29) : 6578 - 6586