共 50 条
- [41] Improvement of performance and data retention characteristics of sub-50nm DRAM by HfSiON Gate dielectric 2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 184 - +
- [42] Investigation of Sub-20nm 4th generation DRAM cell transistor's parasitic resistance and scalable methodology for Sub-20nm era 2023 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS, 2023,
- [44] Extracting Opinionated (Sub) Features from a Stream of Product Reviews DISCOVERY SCIENCE, 2013, 8140 : 340 - 355
- [45] Sub 90nm DRAM Patterning by using modified chromeless PSM at KrF lithography era. Optical Microlithography XVIII, Pts 1-3, 2005, 5754 : 1388 - 1394
- [46] Electrical characterization of sub-100nm features in semiconductor devices 2006 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2006, : A6 - A6
- [47] Large-scale lithography for sub-500nm features INTERNATIONAL MEMS CONFERENCE 2006, 2006, 34 : 34 - 38
- [48] Investigation of full-field CD control of sub-100 nm gate features by phase-shift 248-nm lithography METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XV, 2001, 4344 : 334 - 343