Interposers for Power Supply Voltage Noise Reduction

被引：0

作者：

Uematsu, Yutaka ^{[1
]}

Yagyu, Masayoshi ^{[1
]}

Osaka, Hideki ^{[1
]}

机构：

[1] Hitachi Ltd, Yokohama Res Lab, Yokohama, Kanagawa, Japan

来源：

2012 IEEE 21ST CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS | 2012年

关键词：

component; power delivery network; self impedance; transfer impedance; electromagnetic bandgap; interposer;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This report proposes low power supply noise interposers with two types of structures based on embedding technologies. These structures reduce (i) self-noise and (ii) transfer-noise. We designed and developed these two structures and evaluated them experimentally. Using small chip components (0402) permitted interposer heights of less than 0.6 mm. The measurement results indicate the following: (i) reductions of on-chip power supply noise on the order of several hundreds of MHz; (ii) S21 less than -60dB achieved from 10 MHz to a few GHz.

引用

页码：264 / 267

页数：4

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