Low power VLSI design: An optimal binding algorithm in high-level synthesis using integer linear programming

被引：0
|
作者：
Shiue, WT [1 ]
机构：
[1] Oregon State Univ, Dept Elect & Comp Engn, Corvallis, OR 97331 USA
来源：
6TH WORLD MULTICONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL XV, PROCEEDINGS: MOBILE/WIRELESS COMPUTING AND COMMUNICATION SYSTEMS III | 2002年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present an optimal low-power binding algorithm based on linear programming model. A novel parallel graph (PG) is constructed and used for the development of our LP model. Once the PG is created, linear programming techniques are used to search all paths through the PG to find the optimal binding that minimizes the overall power consumption due to switching activity. We benchmarked our algorithm on two applications, a second-order differential equation solver (DiffEq) and a finite impulse response filter (FIR). In our experiments, the power consumption of the DiffEq was reduced by 8.2%. Power consumption for a FIR fitter sharing three multipliers and three adders was reduced by 18.5% while the same FIR sharing two multipliers and two adders achieved a 32.2% power reduction.
引用
收藏
页码：458 / 461
页数：4
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