Data path allocation for low power in high-level synthesis

This paper presents an approach for data path allocation in high-level synthesis aiming at power reduction. In this approach, the register allocation and module allocation are performed in the same phase in polynomial time. The power consumption is reduced by minimizing the functional switching activities and switched capacitance of the implementation architecture. The experimental results confirm the viability and usefulness of the approach in minimizing power consumption while keeping the number of registers and interconnections to the optimal.