A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity

被引：0

作者：

Fujieda, Naoki ^{[1
]}

Ayuzawa, Yusuke ^{[1
]}

Hongo, Masato ^{[1
]}

Ichikawa, Shuichi ^{[1
]}

机构：

[1] Toyohashi Univ Technol, Dept Elect & Elect Informat Engn, Toyohashi, Aichi, Japan

来源：

PROCEEDINGS OF TENCON 2018 - 2018 IEEE REGION 10 CONFERENCE | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a case for intra-module multiple clock domain design in FPGAs using a high-radix Montgomery multiplier. Our design aims at simple hardware description from algorithm description, avoiding the decrease of clock rate by a long combinatorial path. According to our evaluation with 1024-bit modular exponentiation units, the calculation time reduced by 1.0% on average. The additional logic units for the proposed design was 2,556 LUTs and 1,043 flip-flops per multiplier at a maximum.

引用

页码：1489 / 1492

页数：4

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