CMP-less ILD0 Planarization Technology for Gate-last Process

As CMOS technology scales to 32nm node and beyond, ILD0 planarization is one of critical technologies in high-K metal gate-last process integration. In this paper, a novel sub-micron gate-last process featuring with CMP-less spin-on glass/silicon oxide (SOG/SiO2) etch-back method was demonstrated for low cost logic platform. The innovative approach of SOG two steps plasma etch-back with O-2 treatment can be successfully used for ILD0 planarization of gate-last process. SEM results indicated that there was fairly little "dish effect" and step height close to zero on the 0.4 mu m gate-stack array and finally achieved a good planarization on the whole substrate.